1. Field of the Invention
This invention relates to circuit configurations and the technological process for obtaining logic LSIs which can be used in various kinds of applications, and, more particularly, relates to programmable logic devices (PLDs).
2. Description of the Prior Art
Gate arrays and PLDs are used as logic LSIs which can be manufactured to a certain stage with the same process steps regardless of their individual application, and the circuit of each of which can be modified in accordance with the individual application.
Generally, gate arrays are manufactured with the same steps to the stage preceding the steps in which metal layers are formed, and thereafter three steps of forming two metal layers and contact holes (also called through holes, or vias) connecting the two metal layers with each other are performed using masks which are specially patterned to comply with the requirements of individual application, thereby obtaining logic LSIs each of which conforms with the individual application.
A PLD generally comprises an AND array for obtaining a logical product (AND) of input signals from a plurality of inputs, and an OR array for obtaining a logical sum (OR) of signals on the output lines of the AND array. The outputs of the OR array are transmitted as output signals of the PLD. In some PLDs, a part of the outputs of the OR array is sent to flip-flops the output of which is fed back to the input of the AND array. The logic of both or either of the AND and OR arrays can be set in accordance with the purpose of the PLD. In many cases, the logics of the AND array and OR array are set by disconnecting fusible metal links.
When manufacturing a conventional gate array, photomasks for three process steps (i.e., the formations of the first metal layer, the second metal layer and the contact holes connecting the two metal layers) are required for each application. Such metal steps should be followed by other process steps. As a result, many working hours are necessary for preparing three photomasks and performing the other process steps, causing the problem that the market requirement of the short period of delivery cannot be satisfied.
As described above, in conventional PLDs, logics are realized only by combining AND arrays and OR arrays so that rather complicated logics are difficult to realize, resulting in impaired flexibility of realizing logics.